/*
 * File   : tx_top.v
 * Date   : 20171111
 * Author : Bibo Yang, rspwfpgas@163.com
 *
 */

`timescale 1ns/1ns
module tx_top (
    input  wire         rst,
    input  wire         clk,
	
    input  wire         phy_giga_mode,
    output wire         gen_en,  // multicycle timing control signal

    input  wire [31: 0] int_data_i,
    input  wire         int_valid_i,
    input  wire         int_sop_i,
    input  wire         int_eop_i,
    input  wire [ 1: 0] int_mod_i,

    `ifdef ENABLE_INTERNAL_PHY 
    output wire          gmii_txclk ,
    output wire          gmii_txctrl,
    output wire [ 7: 0]  gmii_txdata
    `else
	`ifdef ENABLE_TX_GMII_SIGS
    input  wire          gmii_txclk , 
    input  wire          gmii_txctrl,
    input  wire [ 7: 0]  gmii_txdata,
	`endif
    output wire         rgmii_txclk ,
    output wire         rgmii_txctrl,
    output wire [ 3: 0] rgmii_txdata
    `endif

);

`ifdef ENABLE_TX_GMII_SIGS
`else
wire          gmii_txclk ; 
wire          gmii_txctrl;
wire [ 7: 0]  gmii_txdata;
`endif

`ifdef ENABLE_INTERNAL_PHY
`else
// gmii to rgmii converter
gmii2rgmii gmii2rgmii_inst(

    .gmii_clk  ( gmii_txclk ),  //input  wire        
    .gmii_den  ( gmii_txctrl),  //input  wire        
    .gmii_dout ( gmii_txdata),  //input  wire [ 7: 0]

    .rgmii_clk (rgmii_txclk ),  //output wire        
    .rgmii_den (rgmii_txctrl),  //output wire        
    .rgmii_dout(rgmii_txdata)   //output wire [ 3: 0]
);
`endif

// streaming to gmii converter
tx_gearbox tx_gearbox_inst(
    .rst          (        rst  ),  //input  wire         
    .clk          (        clk  ),  //input  wire  
	
    .phy_giga_mode(phy_giga_mode),  //input  wire         
    .gen_en       (       gen_en),  //output reg  
	
    .int_data_i   (  int_data_i ),  //input  wire [31: 0] 
    .int_valid_i  (  int_valid_i),  //input  wire         
    .int_sop_i    (  int_sop_i  ),  //input  wire         
    .int_eop_i    (  int_eop_i  ),  //input  wire         
    .int_mod_i    (  int_mod_i  ),  //input  wire [ 1: 0] 
	
    .gmii_clk     (  gmii_txclk ),  //output wire         
    .gmii_ctrl    (  gmii_txctrl),  //output reg          
    .gmii_data    (  gmii_txdata)   //output reg  [ 7: 0] 
);

endmodule
